SELCC=CAP0RISING, CIS=CAPTURE_CHANNEL_0, CTM=TIMER_MODE
Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.
| CTM | Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer’s Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000. 0 (TIMER_MODE): Timer Mode. Increments every rising PCLK edge 1 (RISING): Counter Moderising edge. . TC is incremented on rising edges on the CAP input selected by bits 3:2. 2 (FALLING): Counter Mode falling edge: TC is incremented on falling edges on the CAP input selected by bits 3:2. 3 (DUAL): Counter Mode dual edge: TC is incremented on both edges on the CAP input selected by bits 3:2. |
| CIS | Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Value 0x3 isreserved. 0 (CAPTURE_CHANNEL_0): Capture channel 0. 1 (CAPTURE_CHANNEL_1): Capture channel 1. 2 (CAPTURE_CHANNEL_2): Capture channel 2. |
| ENCC | Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs. |
| SELCC | Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved. 0 (CAP0RISING): Rising Edge of thesignal on capture channel 0 clears the timer (if bit 4 is set). 1 (CAP0FALLING): Falling Edge of thesignal on capture channel 0 clears the timer (if bit 4 is set). 2 (CAP1RISING): Rising Edge of thesignal on capture channel 1 clears the timer (if bit 4 is set). 3 (CAP1FALLING): Falling Edge of thesignal on capture channel 1 clears the timer (if bit 4 is set). 4 (CAP2RISING): Rising Edge of thesignal on capture channel 2 clears the timer (if bit 4 is set). 5 (CAP1FALLING): Falling Edge of thesignal on capture channel 2 clears the timer (if bit 4 is set). |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |